1. Technical Field of the Invention
The present invention relates to an improved digital Delay/Phase Lock Loop (DLL/PLL) with a duty cycle locking mechanism. More specifically the present invention provides an apparatus for enabling duty cycle locking at the rising/falling edge of the clock.
2. Description of Related Art
A PLL or DLL is extensively used in large digital chips like a System on a Chip (SOC), microprocessors, memories, and the like, to cancel the on chip clock amplification and buffering delays, and to improve the I/O timing margins. A DLL is preferred over a PLL as the increasing clock speeds and increasing levels of complexity in digital circuits create a hostile operating environment for phase alignment circuits.
Analog DLLs have been employed in the past to perform synchronization. Such analog DLLs comprise a delay chain having a delay of its elements being varied by analog bias voltages supplied by a phase detector. In digital systems, such as memories, microprocessors and application specific integrated circuits, these types of DLLs introduce analog design complications in a mainly digital design and therefore are avoided.
To overcome the above-mentioned complications, digital DLLs were developed that use a digitally adjustable delay line. Digital information is used to either include or exclude a certain number of delay elements within a delay chain. Although digital DLLs have a much higher jitter than analog DLLs, their ease of implementation in the digital system makes them a preferred solution in most digital applications.
The block diagram for a conventional digital DLL is illustrated in FIG. 1. The DLL comprises a DLL/PLL 4 receiving at a first input the external clock. The output DLLOUT of the DLL/PLL 4 is connected to the input of a clock tree 5. The output of the clock tree 5 is fed back as signal FEEDCLK to a second input of the DLL/PLL 4. The problem with a conventional DLL 4 is that the input clock (EXTCLK) has to pass through long delay chains and other logic. Secondary effects on semiconductor delays and logic devices alter the shape of the input clock EXTCLK pulse and hence, the duty cycle of the output clock DLLOUT is not the same as that of input clock.
The problem of altered duty cycle in a DLL is illustrated with the help of the waveforms shown in FIG. 2. It can be observed that output of the prior art DLL, the signal DLLOUT, has a different duty cycle when compared with the input external clock, signal EXTCLK, received by the DLL/PLL 4. Similarly, in case of phase and frequency locking PLLs, the duty cycle is dependent on the VCO clock. So it is impossible to get the same duty cycle of the output clock as that of the input clock.
This change in duty cycle may not be a problem in chips operating on only one clock edge (either the falling or rising edge) as the period of the clock remains unaltered and hence one of the PLL/DLL output clock edges can be synchronized with the input external clock edge for the chip operation. However, this is a critical problem in high performance digital chips, which perform operations on both the falling and rising clock edge. As both edges cannot be synchronized due to alteration in duty cycle, the chip may produce erroneous output because the devices using the external clock (such as I/O ports and the like) may perform an operation before/after an operation is performed on a device using the internal clock (such as logic blocks, memory and the like). For example, in high performance DDR memories, where read and write operations occur at both rising edge and falling edge of the clock having some duty cycle (other than that of 50%), an external clock may result in new input being sampled by the I/O port before the memory is able to write the previous data in a memory location. Thus it is necessary to preserve the duty cycle of the input clock since an altered duty cycle of the input clock may result in erroneous operation in cases where both clock edges are used for chip operations.
United States Patent Application publication number 2003/0218486 describes a digital DLL for correcting the duty cycle. The digital DLL apparatus for correcting a duty cycle includes: a buffer for producing a clock input signal; a delay line unit for receiving/delaying the clock input signal and outputting the clock input signal; a blend circuit for bypassing the first clock signal or producing a blended clock signal; a delay model unit for compensating a time difference of an external clock and an internal clock and generating a compensate clock signal; a direct phase detector for generating a first comparison signal; and a phase detector for generating a second comparison signal. The disclosed apparatus corrects the duty error by using the blend circuit and generates an internal clock signal having 50% of the duty cycle.
The main problem with the conventional DLL arises when the duty cycle of the input clock is not 50% as the DLL is unable to set the duty cycle of the output clock other than at 50%. Although proper sizing of the delay chain and other logic blocks in the clock path can preserve the duty cycle, the process variations would cause a disturbance in the duty cycle. Furthermore, the sizing of the same may have to be varied for different processes. This acts as a limitation to the use of DLL/PLL.
Hence, there is a need for DLLs/PLLs that provide duty cycle locking for input clocks having duty cycle other than 50%. Additionally, there is also a need for a DLLs/PLLs whose duty cycle is process independent.